1. Field of the Invention
The invention relates generally to a bus architecture in a computer system and, more particularly, to an improved bus architecture having two or more bus arbiters and enabling both concurrent data communications between independent bus masters and independent bus slaves.
2. Description of the Related Art
In system-on-a-chip (SOC) systems that utilize a processor local bus (PLB) protocol and a single PLB bus arbiter, requests for read followed by read (xe2x80x9cread-readxe2x80x9d) and write followed by write (xe2x80x9cwrite-writexe2x80x9d) are xe2x80x9cblockingxe2x80x9d in that the data tenures are serialized. This blocking results from sequential in-order address tenures. In the case of a single bus master requesting read-read or write-write to the same or different bus slaves, the resultant serialized accesses are expected and required to maintain sequential ordering consistency. In the case of independent bus masters attempting to access separate and independent bus slaves, the single PLB approach forces the sequential ordering on both the address and data busses. In the case of independent bus masters accessing independent bus slaves, however, it is desirable, for optimal performance, to allow the individual, independent request address and data tenures to execute concurrently and be non-blocking. This allows simultaneous transfers, in the same direction, to occur between independent pairs of bus masters and bus slaves.
Therefore, there is a need for a bus architecture that enables concurrent data communications between independent bus masters and independent bus slaves
In one embodiment of the present invention, a system is provided to include a first bus master and a second bus master. A first bus arbiter is coupled to the first and the second bus masters. A second bus arbiter is coupled to the first and the second bus masters. A first bus slave is coupled to the first bus arbiter. The first bus master requests a first data operation on the first bus slave via the first bus arbiter. The first data operation is performed during a first period. A second bus slave is coupled to the second bus arbiter. The second bus master requests a second data operation on the second bus slave via the second bus arbiter. The second data operation is performed during the first period.